The present invention relates to microelectronic packaging.
A typical semiconductor chip is formed as a generally thin, rectangular solid having front and rear major surfaces and small edge surfaces extending between the front and rear surfaces. The thickness or distance between the front and rear surfaces of the chip typically is many times smaller than the length and width of the chip measured in the plane of the front surface or rear surface. The chip typically has contacts on its front surface and electronic circuitry within the chip connected to the contacts. In use, the contacts are electrically connected to a larger circuit. Ordinarily, chips are manufactured by treating a larger, flat wafer to form the electronic circuitry and contacts of numerous chips simultaneously, and then severing the wafer along lines referred to as “dicing lanes” which form the edges or boundaries of the individual chips.
Chips typically are mounted in structures referred to as packages. A package may include a package substrate such as a small circuit panel having terminals thereon. The chip is physically attached to the package substrate, and the contacts of the chip are electrically connected to the terminals of the package substrate. The package substrate, with or without other components, provides physical protection for the chip. Moreover, the terminals of the package substrate are arranged so that the package as a whole can be readily mounted to a circuit panel or other structure to provide the interconnection between the chip and the larger circuit. For example, many chip packages have terminals that may be larger than the contacts of the chip, spaced apart from one another at larger intervals than the contacts of the chip, or both, so that the terminals can be soldered readily to conduct structures on a larger circuit panel using standard bonding techniques such as surface mounting. For example, the terminals on a chip package may be arranged in a pattern corresponding to a formal or informal industry standard such as those published by the JEDEC Solid State Technology Association.
Certain semiconductor chips are provided with their contacts disposed in one or more columns extending in a column direction along the front face of the chip. Typically, the column direction is parallel to two edges of the chip. For example, the column or columns of contacts may be disposed midway between the left and right edges of the chip and may be parallel to the edges of the chip. Memory chips such as dynamic random access memory (“DRAM”) chips commonly are provided in this configuration. Chips of this type commonly are packaged using a package substrate having upper and lower surfaces, terminals at the lower surface, and an aperture in the form of an elongated slot extending through the substrate from the upper surface to the lower surface. The substrate may have bond pads at the lower surface adjacent the slot, the bond pads being electrically connected to the terminals by traces on the package substrate. The chip is mounted to the upper surface of the package substrate with the front face of the chip facing downwardly toward the package substrate and with the column or columns of contacts on the chip aligned with the slot in the package substrate. The contacts of the chip are connected to the bond pads of the package substrate by wire bonds extending through the slot in the package substrate, so that the contacts of the chip are electrically connected to the terminals of the package substrate. The wire bonds typically are covered by an encapsulant, which fills the slot. The terminals at the lower surface of the package substrate can be bonded to contact pads on a circuit panel so that the chip is interconnected with a larger circuit incorporated in the circuit panel.
Memory chips commonly are used in sets. For example, in a computer system that handles data in the form of eight-bit bytes and that uses a single error correction bit for each byte, the memory chips may be provided as sets of nine memory chips, so that a byte and the accompanying error correction bit can be stored and retrieved by storing or retrieving one bit to each of the nine chips. The chips of such a set may have many of their contacts connected on common. For example, the contacts that carry power supply voltages and ground can be connected in common, as well as the contacts that carry address and data signals to the various chips. Other contacts on each chip have unique connections to unique lines on the circuit panel. For example, signals referred to as “chip select” signals used to denote an individual chip of the set typically have unique connections on the circuit panel, so that a signal sent to a particular contact pad on the circuit panel is routed to only one chip of the set.
Various proposals have been advanced for mounting plural chips of this type in packages so that the plural chips can be connected to a circuit panel by attaching one package to the circuit panel. Such a package may have some of the contacts of each chip connected on common to terminals on the package substrate. This reduces the number of connections that must be made between the chip packages and the circuit board. For example, where two chips are provided in a single package, the total number of terminals on the package may be considerably less than twice the number of terminals that would be required on a single chip package. The terminals that can be connected in common to the two chips in the package need be provided only once. Moreover, the number of packages that must be handled and mounted to the circuit panel can be reduced by providing multiple chips within each package. For example, U.S. Pat. No. 7,061,121 and U.S. Published Patent Application No. 2012/0267798 disclose packages that can accommodate multiple chips such as memory chips. Nonetheless, further improvement would be desirable.